Principle of operation and performance of 1.3 volt SOI resistor load vertical dual carrier field effect transistor flip flop fabricated for SRAM, FPGA and switching SOC with effective channel length of 30nm

Principle of operation of resistor load SOI vertical dual carrier field effect transistor (VDCFET) flip flop is reviewed. The measured and the calculated results of the performance of the 1.3 volt resistor load SOI VDCFET flip flop, with 30nm effective channel length, are presented. These SOI VDCFET flip-flops are fabricated by using lithographic equipments for linewidths greater than 180nm. These flip flops are being designed as the main building blocks of VDCFET SRAM, FPGA and switching SOC with effective channel length of 30nm.