Layout optimization of spiral inductors in silicon chip for 5.7GHz WLAN

A process to design and optimize the layout structure of inductors has been proposed. A set of inductors working at 5.7 GHz for WLAN has been designed based on using low resistivity silicon substrates and the 0.18 μm Cu/SiO
₂
interconnect technology. The layout structures such as the inner core size, coil-width and coil-space of the inductors (0.2 nH to 11 nH) have been optimized. The optimized Q-value at 5.7 GHz is improved by a factor of 5 - 8 as compared to the tested Q-value of inductors using previous layout.