A 5.8-GHz delta-sigma fractional-N frequency synthesizer for IEEE 802.11a applications

A 5.8-GHz fractional-N frequency synthesizer for IEEE 802.11a WLAN applications is designed in a 0.25μm CMOS process. The synthesizer integrates a low power, high efficient voltage-controlled oscillator (VCO), an injection-locked frequency divider and a digital third-order MASH delta-sigma modulator together. The VCO is capable of 240MHz tuning range and exhibits a phase noise of about -115dBc/Hz at 1MHz offset from the center frequency throughout the tuning range. The synthesizer has a bandwidth of 300KHz for a 35MHz reference and can achieve a close-in phase noise of about -80dBc/Hz while the total power consumption is 35mW from a single 2.5V supply.