A 3.125-Gb/s CMOS transmitter for serial data communications

A transmitter operating at half the clock frequency of the transmission data rate has been designed with a 0.25μm CMOS technology. It includes a 10:1 multiplexer to serialize 10-bit wide parallel signals to a 3.125Gb/s data stream and a frequency synthesis PLL to generate clock signals for the multiplexer. To verify the design ideas, some of the key components of multiplexer and PLL were fabricated in 0.25μm CMOS process. Tested on wafer, these chips operate stably and obtain the prospective results. The simulation and experiment results demonstrate the transmitter is suitable for high-speed applications and consumes relatively low power dissipation.