Design of low power high linearity front-end circuit with a novel LNA architecture

A low-power high-linearity front-end circuit with a novel low-noise amplifier (LNA) architecture based on CMOS 0.18μm process is presented in this paper. The conversion gain of the proposed front-end circuit is mainly boosted by current-enhanced technique and current-bleeding technique. To improve the linearity and noise, a complementary common-gate LNA is employed. The proposed front-end circuit achieves measured conversion gain of 18.4dB and input third-order intercept point (IIP
₃
) of -6 dBm under consuming power of 9.4 mW from 1.8V supply voltage. The noise figure is 8.4 dB at 100 MHz IF frequency. The size of the chip is 0.767mm × 0.96mm.