A 7.6 K-gate Josephson macrocell array

The design and technology for a high-speed Josephson macrocell array are described. A macrocell array including 7.6 k gates was fabricated using a 1.5-μm Nb Josephson process. The chip dimensions are 5×5 mm, and its power consumption is 23 mW. An average gate delay in full adder of 5.3 ps has been achieved using the macrocell