A manufacturable 2.0 micron pitch three-level-metal interconnect process for high performance 0.8 micron CMOS technology

Advanced CMOS ASICs require three-level-metal (TLM) capability, while double-level-metal (DLM) technology remains as the standard for logic circuits and high-performance memory applications. The challenges for multilevel interconnect systems are low defect density, high manufacturability, and product reliability. A TLM technology is described that has 2.0-μm-pitch first and second metals using aluminum alloy with 4% copper that meets these requirements. It has been demonstrated in the fabrication of a 90-MHz RISC CMOS CPU with a 1.4×1.4 cm
²
chip size