A 1.28 μm2 bit-line shielded memory cell technology for 64 Mb DRAMs

The technology used to fabricate high-speed and low-power 64-Mb DRAMs (dynamic random access memories) is described. The memory cell developed is a high-storage capacitance bit-line shielded stacked capacitor (STC) cell in which the storage capacitor is formed over the bit-line and a cylindrical storage node structure is used for low-voltage memory operation. The main features of the technology are low-resistance bit-line wiring to achieve short access time of the DRAM, and a simple process to fabricate the cylindrical storage node using poly-Si chemical vapor deposition (CVD) on polyimide layer to obtain large storage capacitance. The usefulness of the technology has been verified by fabricating an experimental 64-Mb DRAM