RIPAC: a VLSI processor for speech recognition

RIPAC is a VLSI processor for dynamic time warping (DTW), devoted to both isolated-word and connected-speech recognition. It works with both the template-matching and the discrete hidden-Markov-model approaches. The chip is organized in a Harvard architecture with a microprogrammed control unit and an independent data path, devoted to both the dynamic programming task and the external address generation. The external data RAM can be addressed, up to 16 Mbytes, with a compaction of information. An internal cache relaxes speed requirements for the external data memory. Testing solutions are implemented for either system or circuit functionality; a test microprogram is cabled in the microprogram ROM. The chip works at a frequency of 16 MHz with a microinstruction cycle of 125 ns. Working chips have been produced using a 3-μm double-metal CMOS technology with a full custom approach. RIPAC has a complexity of 70 K equivalent transistors, a die size of 6 mm×6.5 mm, housed in a 68-pin LCC package, and a power dissipation of about 300 mW at 16 MHz