A 65nm CMOS fully integrated 31.5 dBm triple SFDS Power Amplifier dedicated to W-CDMA application

This paper presents a 65nm CMOS-Power Amplifier (PA) designed for UMTS standard. It is based on a triple Stacked Folded pseudo-Differential Structure (triple SFDS) power stage and a differential cascode driver stage. The PA provides 31.5 dBm maximal output power (P
_max
) with 20% of maximal power added efficiency (PAE
_max
) at 1.95 GHz. The linear gain is 37 dB and the compression point (OCP1) is 29.5 dBm. In order to fulfill the W-CDMA requirements, the PA respects the ACLR requirements until 23 dBm.