Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuit

A 1.2V 1.95mW low-power Programmable Gain Amplifier (PGA) with high-input range is proposed and implemented in a 90nm CMOS process. The PGA is formed by three stages with a bandwidth of 20MHz for a 2pF capacitive load. Gain is in the range between 0 and 72dB in steps of 6dB. The stage core consists in a differential super-source follower (SSF) with programmable resistive degeneration. Each stage uses a front-end capacitive decoupling network which allows a robust selection of the operating point for improving linearity and reducing power. Further power saving is achieved with a common-mode feed-forward circuit (CMFFC), based on a simple current conveyor. The total PGA area is 165×33μm
²
in a 90nm CMOS process. Post-layout simulations at maximum gain show a THD of -57dB and -42dB for output amplitudes of 0.6V
_pp
and 1.2V
_pp
, respectively. Input referred noise is just 10.2nV
_rms
/√Hz from 1MHz to 4MHz.