Asymmetric cross-coupled sense amplifier for small-sized 0.5-V gigabit-DRAM arrays

A new sense amplifier (SA) and relevant circuits were proposed for low-power, high-speed, and small-sized 0.5-V gigabit DRAM arrays. The SA, consisting of a low-V
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NMOS preamplifier and a cross-coupled high-V
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PMOS latch, achieved 46% area reduction compared to our previously proposed SA with a low-V
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CMOS preamplifier. Separation of the SA and a data-line pair, and overdrive of the latch achieved a restoring time of 13.4 ns and a sensing time of 6 ns. An adaptive leakage control of the preamplifier reduced the leakage current of the SA to 2% of that without the control.