A sub-mW all-digital signal component separator with branch mismatch compensation for OFDM LINC transmitters

This paper presents a sub-mW all-digital signal component separator (SCS) with a novel branch mismatch compensation scheme for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. This chip is manufactured in 90nm standard CMOS process with active area 0.06mm
²
. The DCPS can generate phase-modulated signal at IF 100MHz with 8-bit resolution and RMS error 9.33ps (0.34°). The phase calculation can be operated with maximum 50MHz speed at 0.5V supply voltage, resulting in 73.88% power reduction, and the overall SCS power is only 949.5μW. With the aid of this SCS, the branch mismatch compensation scheme provides 0.02dB gain and 0.15° phase fine-tune resolution. The system EVM with 64-QAM OFDM signals is -29.81dB, and the spectrum can pass the mask test of IEEE 802.11a.