A 28 nm dual-port SRAM macro with screening circuitry against write-read disturb failure issues

We propose a circuit technique for an 8T dual-port (DP) SRAM in order to screen degraded minimum operating voltage (V
_min
) due to the write/read disturb issue. This circuitry allows us to generate the write/read disturb condition without relying on the conventional costly asynchronous operation. We designed and fabricated a 512-kb DP-SRAM macro using 28-nm low-power CMOS technology, and confirmed assured screening of failures in the write/read disturb operations.