Analysis and optimization of mismatch and parasitics in pipelined ADCs

The mismatch and parasitics of layout and process in pipelined ADCs are analyzed in this paper and an optimized system has been implemented. Based on the model establishment of the proposed ADC, the offset of input in each stage and the fluctuation of reference voltage, which degrades the effective resolution of pipelined ADCs, caused by transistors mismatches and parasitic effects are modeled and estimated. The error bounds are also derived to optimize the ADC's properties. After careful design in schematic and layout, a 12bit pipelined ADC is realized in a commercial CMOS 0.35μm process. The post layout simulations show that the circuit achieves 69.3dB signal-to-noise-and-distortion ratio (SNDR), 80.1dB spurious free dynamic range (SFDR) and -80.1dB total harmonic distortion (THD) operating up to the 40MHz sampling clock, which proves the beneficial of the analysis and optimization.