Impact of the storage layer charging on Random Telegraph Noise behavior of sub-50nm charge-trap-based TANOS and floating-gate memory cells

Random Telegraph Noise (RTN) characterization was performed on charge-trap-based TANOS memory cells. The analysis results of cycle stress dependence and cell size scaling are discussed based on single cell measurements. Comparing charge-trap and floating-gate memory technologies different behavior for RTN was obtained. On charge-trap cells a threshold voltage dependence and superimposed noise was observed and is discussed based on measurement results and different cell architectures.