A novel floating body cell memory with a laterally engineered bandgap using a Si-Si:C heterostructure

A lateral bandgap engineered floating body cell (FBC) memory is demonstrated for the first time; it features a high-k gate dielectric, a metal gate, and an epitaxially grown Si
0.99
C
0.01
S/D. Design of valence band offset and incorporation of strain effects are achieved from a heterogeneously mismatched lattice for S/D regions. The figures of merit in the FBC memory, particularly the retention time, operational voltage, signal sensing margin, and non-destructive read operation, are remarkably enhanced under various operating conditions.