Device and circuit interactive design and optimization beyond the conventional scaling era

Summary form only given. Miniaturization of device feature size has improved both device density and device performance in the conventional scaling era. However, degradation of electrostatic gate control, increasing contribution of parasitics, and increasing power consumption have limited scalability. The slow-down of L
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scaling has been compensated for by technology features such as strain engineering, high-κ dielectric, and novel channel materials and device structures. Looking forward, new trends for device design are expected. Particularly, considerable amount of attention is needed in 1) parasitics, and 2) understanding device design and its impact on the circuit-level environment. For advanced technologies and emerging devices, technology development and device design has to be revisited, as conventional methods of performance benchmarking are unable to capture the system-level power-constrained circuit design tradeoffs. In this paper, several issues on technology development are further addressed based on the study of device and circuit interactive design and optimization.