Process challenges and development of eWLP

Embedded Wafer Level Package (eWLP) is designed and developed. The eWLP consists of one silicon die encapsulated with a mold compound and its size is 12mm × 12mm × 0.2mm. The assembly process of eWLP consists of reconfiguration of the dies on an adhesive tape, followed by molding, thinning and rerouting distribution layer (RDL) process. Finite Element Modeling (FEM) is used to understand the stress distribution in the eWLP and provide design input to the configuration of eWLP. The encapsulated eWLP passed 1000 air-to-air thermal cycles (-40 to 125°C), unbiased Highly Accelerated Stress Test (HAST) and moisture sensitivity level 3 (MSL3) test. In this paper, FEM of eWLP, selection of granular epoxy mold compound (EMC), die shift analysis, and warpage study will be discussed in detail.