Effect of substrate warpage on flip chip BGA thermal stress simulation

In this work, a new empirical method is proposed to incorporate the initial substrate warpage into package stress simulation. As a first step, the bare substrate strip warpage characteristics were mapped. The out-of-plane displacements of the substrate strips were measured as a function of temperature using shadow moiré technique. It was observed that the warpage values of the bare substrate vary predominantly along the length of the strip. Units located at the substrate corners and edges exhibited higher warpage compared to units in the strip center. The higher warpage at units located at the substrate edge could impact the flip chip assembly process and also the stresses at the 1
^st
level interconnect.