A dynamic power-aware process variation calibration scheme

In this paper, a power-aware process variation calibration scheme is proposed. The proposed calibration system provides the ability to detect and control the n- and p-type variations independently through the use of all-n and all-p ring oscillators. Calibration is then carried out through the use of the supply voltage and body bias to alter the device parameters to match those of a certain process corner that is determined by the system designer. This scheme is characterized by its ability to dynamically change the desired mapping target according to the computational load. The calibration system has been implemented and simulated in TSMC 90-nm technology. Simulation results show that the maximum variation in the operating frequency was reduced from 44.3% to 3.1% and worst-case leakage current reduced by 21%. The results also show the system's ability to compensate for dynamic load variations.