Physical design aware selection of energy-efficient and low-energy nanometer flip-flops

In this paper, a comparison of the most representative flip-flop (FF) topologies in a 65-nm CMOS technology is carried out. For the first time in the literature, local wires capacitances are included in the transistor-level design loop, allowing to reach the actual optimum designs, given the huge impact that local interconnects have on both energy and delay (E-D) of FFs. The investigation permits to identify the most suitable FFs for low-energy and energy-efficient circuits in nanometer technologies.