MOS current mode logic realization of digital arithmetic circuits

In this paper, MOS current mode logic (MCML) and dynamic current mode logic (DyCML) techniques are analyzed and applied to the generation of digital arithmetic circuits. A full adder structure is demonstrated, analyzed and compared with equivalent CMOS, Domino and CPL structures and realized using 0.18 μm CMOS technology operating with 1.5 V and -1.5 V supply voltages. Also, a four bit multiplier and a CORDIC block were analyzed and realized using MOS Current Mode Logic. PSPICE simulation results of each realization have been demonstrated.