Control Techniques for Coupling a Coarse-Grain Reconfigurable Array with a Generic RISC Core

This paper presents three different control techniques to couple a Coarse-Grain Reconfigurable Architecture (CGRA) with a generic RISC processor. In the architecture under study the CGRA, i.e., a coarse-grain array, works as co-processor and is used to accelerate a kernel selected by the application developer. The array is meant to perform the data processing operations of the kernel, while the RISC processor takes care of the control of the kernel global execution. The control techniques proposed here do not add any dedicated instructions to the ISA of the RISC processor, but are mostly based on load/store operations. The first method is the slowest one, in which the control operations are executed sequentially with the array processing. The second approach enables some parallelism between control operations and array processing. The parallelism is guaranteed by the replacement of a single control register with a two-register delay chain. The last approach is the fastest, which replaces the delay chain with a FIFO. In particular, a 64-point FFT test case shows that the last solution is 2.5× faster than the second one.