Area-efficient implementation of low bit-depth motion estimation algorithms

In order to meet the processing requirements of real-time low-complexity video compression, this paper proposes an area-efficient low bit-depth representation based full search block motion estimation engine. The source pixel based linear arrays(SPBLA) is adopted for the system-level architecture. Furthermore, towards system bottlenecks which are ROM-based systolic cell and redundant data memory organization, optimized structures are presented. Compared with the hardware in former literatures, the proposed hardware can achieve significant improvement in area and no throughput is lost. Implementation results on Xilinx XC2VP30-7 FPGA show that, at the cost of 6.78% and 6.62% extra consumption of LUTs, ROM and BRAM are no longer needed and 93.75% DP-RAM can be reduced.