A 1.62/2.7Gbps clock and data recovery with pattern based frequency detector for displayport

A clock and data recovery (CDR) for the physical layer of DisplayPort at sink side is described. A 1/5-rate linear phase detector (PD) compares the phase of the incoming data with that of sampling clock to recover a clean clock and data. A pattern based frequency detector (PBFD) reduces frequency error to be in the pullin-range of the 1/5-rate linear PD. The PBFD reduces the frequency error down to 3.2% before the linear PD starts its operation. The CDR implemented in a 0.13 m CMOS process shows 29-ps rms and 154-ps peak-to-peak jitter in the recovered clock and 10
^-7
bit error rate (BER) for 2
³¹
-1 pseudorandom binary-sequence (PRBS) input while consuming 87mW from a 1.2-V supply.