Novel analog synthesis tool implemented to the Cadence design environment

While analog part of the integrated circuit covers 10% of its area its design takes 90% of the time needed to design the whole circuit. Therefore analog synthesis is very hot topic at present. It can save enormous part of the design time. This paper presents work on novel analog synthesis tool capable of choosing circuit architecture and to size its devices by optimization to meet the design specification. This tool is implemented into Cadence design environment to be easily used by the analog designers. The tool is under construction at present so partial results are presented here.