Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters

This paper presents an analysis on energy dissipation of a digital half band filters operated in the the sub-threshold (sub-V
_T
) region with throughput constraints. The degradation of speed in the sub-V
_T
domain is counteracted by unfolding the architectures. A filter is implemented in a basic 12-bit and its various unfolded structures. The designs are synthesized in a 65 nm low-leakage high-threshold CMOS technology. A sub-V
_T
energy model is applied to characterize the designs in the sub-V
_T
domain. The results from application of an energy model shows that the unfolded by 2 architecture is most energy efficient, dissipating 22% less energy compared to it the original filter implementation at energy minimum voltage. Unfolded by 4 architecture, however, is the best for throughput requirements of around 120 K samples/sec to 1M samples/s, as it dissipates less energy than any other implementation in this speed range.