Transient voltage overshoots of high voltage ESD protections based on bipolar transistors in smart power technology

Transient voltage overshoots of a high voltage (20 V) ESD clamp based on bipolar transistors in a smart power technology are studied using different TLP pulse conditions (rise time, voltage amplitude). The physical mechanisms involved during the ESD clamp turn-on are thoroughly analyzed by the mean of TCAD simulations, allowing the definition of a set of design guidelines for the overshoot reduction.