Chip and package co-design for high performance mixed IC

In this paper, we propose an efficient approach to reduce the effect of the Simultaneous Switching Noise (SSN) for mixed System on Chip (SoC). In order to validate the approach, we have designed a 14-bits 100MHz pipeline ADC as an example. Finite Element Method (FEM) and Method of Moment (MoM) are chose to do the electromagnetic extraction of package and bond-wires separately. The proposed approach combines the equivalent lump model with the ADC chip to perform co-design. A RC network is designed to suppress the SSN. As a result of measurement, the SFDR of the ADC's output can reach 84dB at an input clock of 100MHz with an input signal of 10MHz, which coincides with the expectation by this approach.