A high performance junctionless PTGVMOS with native tie for deca- nanometer regime

In this study, we propose a new technology to fabricate pseudo tri-gate vertical (PTGV) MOSFETs without p-n junctions, named junctionless PTGVMOS (JPTGV). According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ~ 60mV/dec, I
_on
/I
_off
~ 10
¹⁰
, and low interface trap density are all achieved. The device without p-n junctions provides an easier way for JPTGV fabrication and it can be employed for use in deca-nanometer regime.