A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing

A 1.5-1.6 GHz dual-loop phase-locked loop in 0.18-μm CMOS locks in 40 μs and draws only 26 mA from 1.8 V. The proposed techniques include a fourth-harmonic mixer that relaxes the secondary PLL requirements, and an auxiliary charge pump that speeds acquisition without affecting steady-state operation. The integrated RMS phase error is 1.1° and the phase noise spectral density is -116.8 dBc/Hz at an offset frequency of 600 kHz. The largest in-band and reference spurs are -83 dBc and -105 dBc at frequency offsets of 500.5 kHz and 37.9 MHz, respectively.