Adapted assembly processes for flip-chip technology with solder bumps of 50 µm or 40 µm diameter

The further miniaturization of electronic packages is driven by a large variety of applications with high requirements on pitch and form factor. This will be conducive to higher I/O-counts and a reduction of the solder bump size. In this work, new cost-efficient solder bumping and adapted assembly technologies for the processing of flip-chips with a pitch of 100 μm (as well suitable for a pitch of 60 μm) and solder ball diameters of 40 μm or 50 μm, respectively, were demonstrated. The wafer bumping has been realized using a highly efficient wafer level solder sphere transfer process. This technology uses a patterned vacuum plate to simultaneously pick up all of the preformed solder spheres, optically inspect for yield, and then transfer them over to the wafer at once. Initially the flip-chips have been assembled automatically on special BT- and FR4-material using reflow soldering and high performance underfill that has been subject of in-depth investigations. Through this, the long term reliability of the lead free solder joints could be increased significantly on state-of-the-art subtractive printed circuit boards (PCBs) with solder mask. But we found, that a solder bump size of 50 μm seems to be the technological limit when tested according to MILSTD883G, method 1010.8, condition B. That is why we investigated the use of alternative substrates for chips with 40 μm solder bumps as well. For cost efficiency reasons, all processes investigated base upon standard processes of the surface mount technology, but are adapted to the requirements of highly miniaturized components. Our results of the reliability tests will be discussed. Additionally, an analysis of the failure mechanism will be presented.