Fine-grained adaptive CMP cache sharing through access history exploitation

Advances in semiconductor technologies have enabled the integration of multiple processor cores as well as varying sizes of L1 and L2 caches on a single chip. The ever growing complexity and diversity of the associated workloads impose a crucial challenge on the organization and management of the on-chip cache resources. As each core generates a varying amount of accesses to each cache line during execution, sharing a single L2 cache among all the cores can minimize off-chip misses. However, each access to a shared L2 cache imposes significant performance and power overhead, as the tags of all the blocks on a cache line need to be compared in parallel. To efficiently utilize cache resources while saving power, we present in this paper a fine-grained L2 cache management technique with minimum hardware overhead. Each core is allowed to set an ownership bit in an L2 cache block to directly signify the necessity of tag checking, thus reducing the latency and power consumption of each cache access. Joint block ownership approaches provide shareability, thus precluding costly data replication from which private L2 caches typically suffer. Meanwhile, through monitoring line-based access histories, a core that produces a large amount of misses is precluded from replacing blocks belonging to other cores, thus efficiently attaining fine-grained cache partitioning. Experimental results confirm that the proposed technique can effectively reduce the access latency and power consumption of traditional shared L2 caches, accompanied by additionally a slight reduction in the miss rate.