Static ultra-low-voltage high-speed CMOS logic and latches

In this paper we present timing details for static ultra-low-voltage (ULV) CMOS inverters and latches. The logic presented resemble domino CMOS logic and is more than 10 times as fast as complementary CMOS for very low supply voltages. Static ULV inverters and latches are presented and preliminary simulated data are provided for a 90 nm TSMC CMOS process.