Reliability study in capacitor less 1T-RAM cells on SOI

We have shown that careful optimization of the write conditions is needed in order to achieve the stringent endurance spec of 10
¹⁶
cycles for 1T-RAM cells without compromising the sense margin and retention. The degradation seen during cycling of the cells can be attributed to the creation of interface states and carrier trapping at either the source (“0”) or drain side (“1”). Overall reduction of the biases, especially VD, will have a beneficial effect on the endurance behavior.