Design of High-Speed DDC Based Multi-stage

This paper presents a multi-stage digital-down-converter (DDC) bases on nπ/4 fixed frequency down-conversion. From the contradiction between high-speed processing and the challenge of FPGAs hardware resources in the typical direct frequency conversion, special design are applied to optimize the mixers and filters for reducing peak processing rate of system. Analysis the frequency remaining in mixing and alias of anti-flod spectrum problem which triggered in multi-stage DDC. The simulation result proves that it supports 240MHz no-alias DDC while low-pass sampling at a low peak processing rate below 120MHz.