Graphical interface for debugging RTL Networks-on-Chip

One problem of Multiprocessor Systems-on-Chip (MPSoCs) based on Networks-on-Chip (NoCs) is tracing the dozens of parallel communications that are transferred in the system. The goals of tracing communications are usually either debugging or monitoring the NoC for design space exploration. On Register Transfer Level (RTL) NoCs the tracing is frequently verified by waveforms, which provides limited useful information about the global status of the NoC. The goal of this work is to improve the tracing capabilities of RTL NoCs and provide a global picture of what is happening in the NoC. This is accomplished by using a Java tool to represent graphically relevant events of the NoC. The input of this tool is a list of relevant events generated by the RTL simulator during the simulation of an MPSoC. The HERMES NoC is used as test case for the tool.