A TLP-based characterization method for transient gate biasing of MOS devices in high-voltage technologies

A method to characterize the dynamic behavior of high voltage MOS devices is presented. It utilizes TLP measurements to determine the MOS output characteristics with fixed gate voltages and with floating gates. It characterizes the gate-coupling effect that is defined by the ratio of the device capacitances. This is relevant for design of ESD circuits and compact modelling. Characterization of HV devices in a 0.35um 60V BCD technology illustrates the method.