A 1.7-mW dual-band CMOS frequency synthesizer for low data-rate sub-GHz applications

In this paper, an ultra low-power wideband frequency synthesizer is demonstrated in a 90-nm CMOS technology. The circuit is intended for low data-rate sub-GHz transceivers and is based on a programmable integer-TV phase-locked loop. The frequency synthesizer in cooperation with divide-by-two frequency dividers is able to provide quadrature LO signals in the 300-470 MHz and 750-950 MHz RF bands with a 150-kHz frequency step. It provides a phase noise better than -91 dBc/Hz at 150-kHz offset frequency for all the supported channels. The measured settling time is around 350 μS and the reference spurs are lower than -48 dBc. The power consumption of the frequency synthesizer is only 1.7 mW from a 1.2-V supply.