Fin-height controlled PVD-TiN gate finFET SRAM for enhancing noise margin

PVD-TiN gate FinFET SRAM half-cells with different β-ratios and fin-height controlled transistors have successfully been fabricated using orientation-dependent wet etching and selective recess RIE. It was found that read static noise margin (SNM) increases significantly by controlling β from 1 to 2. With further increasing β, read SNM increases slightly. On the other hand, write margin shows weak dependence on β. By controlling the fin-heights of pass-gate (PG) and pull-up (PU) transistors to one-half pull-down (PD) transistors, i.e., β = 2, the read SNM was enhanced from 133 to 185 mV at V
_DD
= 1 V. Scaled recess areas down to 103 nm square for low-fins have successfully been fabricated by optimized electron-beam lithography and RIE. The developed fin-height controlled technology is very useful for the fabrication of scaled SRAM without cell area increment.