Dual channel and strain for CMOS co-integration in FDSOI device architecture

We report an original Dual Channel-On-Insulator (DCOI) Fully Depleted CMOS architecture by co-integrating nFETs on sSOI and pFETs on Si/SiGe/(s)SOI with a TiN/HfO
₂
gate stack (EOT=1.15 nm) and down to 40 nm gate lengths. We demonstrate for the first time large gains for transconductance (up to +125%) and mobility (+100%) even for short channel pFETs. This enables us to improve the ON(OFF) pFETs trade-off (I
_ON
+23% for a given I
_OFF
=100nA/μm), and thus to obtain similar I
_ON
for n & pFETs (~650μA/μm at V
_DD
=1V). Meanwhile, thanks to a channel material/strain engineering, the threshold voltages are adjusted (V
_th
~+/-0.2V) for high performance (HP) CMOS with a single mid-gap metal gate.