Layout-dependent proximity effects in deep nanoscale CMOS

As CMOS scaling extends into the nanoscale regime, designers need to be aware that device behavior depends not only on traditional geometric parameters such as channel length and width, but also on layout implementation details of the device and its surrounding neighborhood. The advent of stress engineering, in which intentional mechanical stress is applied to improve device performance, also adds new geometric dependencies. This paper reviews the major process technology features that cause layout-dependent proximity effects and how to account for these effects in circuit and layout design.