SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration

Conversion from dc to the 10th Nyquist band is enabled in a SHA-less, 10-b, 100-MS/s pipelined ADC by digitally calibrating the clock skew in the 3.5-b front-end stage. Architectural redundancy of pipelined ADC is exploited to extract skew information from the first-stage residue output with two out-of-range comparators and some simple digital logic; a gradient-descent algorithm is used to adaptively adjust the timing of the front-end sub-ADC to synchronize with that of the S/H. The 90-nm prototype consumes 12.2 mW and digitizes inputs up to 480 MHz (limited by testing equipment) without skew errors in experiments, whereas the same ADC fails at 130 MHz when the calibration is disabled. The measured SFDR is 71 dB at 20 MHz and 55 dB at 480 MHz.