High-performance energy-efficient arithmetic circuits using Weighted Logic

In the following paper, a new approach for de signing high-performance arithmetic circuits based on the new “Weighted Logic” family is presented while demonstrating the new technique's performance advantage an d relatively low-energy characteristics. It will be shown by the means of a 64-bit comparator and a 64-bit adder that using the new approach, arithmetic functions can be implemented more efficiently than state-of-the-art designs in terms of speed and energy consumption.