An automated methodology for implementing a DFM-aware standard cell library under process window and context variations

As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. Therefore the litho-contour based extraction flow has become a candidate to accurately capture the process variations. This paper presents a proposal for a software framework to enhance the manufacturability of the traditional standard cell library. The novel method is a fully automated litho-aware, context-aware and Resolution Enhancement Techniques (RET)-aware standard cell characterization. A digital circuit that consists of 230 standard cells is re-designed by using the DFM-aware library. The results indicated a robustness against process sensitivity that is 24% better than that of same design using traditional library.