A low-power, small-area voltage reference array for a wafer-scale prototyping platform

A programmable voltage reference used in an advanced wafer-scale hierarchical voltage regulation circuit is presented. The novel arborescence structure of the voltage regulation system is described and the requirements for the voltage reference derived. The proposed programmable voltage reference is based on beta-multiplier architecture, implemented in 0.18 μm CMOS technology with a very small area of 0.0014 mm
²
. It provides several output voltage references between 1.0 and 2.5 V from an input voltage between 3.0 and 4 V. The overall divergence is less than 10 % from desired output levels, which makes the use of a complete bandgap non-essential for our application. We gave priority to fit in the small allowed area with limited power consumption. The total power consumption of the whole voltage reference module is 386 μW and its static power consumption drops to 0.66 nW when turned off.