Acceleration of Backtracking Algorithm with FPGA

The standard approach to the Backtracking Algorithm is to use any programming language and code that in a sequential manner. The work describes the implementation of a fast computation of the Backtracking Algorithm with FPGA (Field Programmable Gate Array) logic. The specific problem is then encoded into the FPGA structure and solved in the hardware. Each partial candidate of the solution is then put / rejected in a single clock cycle only. The results of the method are demonstrated on the simplified “Eternity II” puzzle.