Advanced CMOS protection device trigger mechanisms during CDM

The charged device model (CDM) is now considered to be an important stress model for defining electrostatic discharge (ESD) reliability of integrated circuit (IC) chips. This paper examines the CDM performance for three different advanced protection devices in an 0.35-/spl mu/m LDD complementary metal-oxide semiconductor (CMOS) technology. Through failure analysis and device simulations, the behavior of these protection devices during the CDM event is investigated. The results will enable devices to be designed for improved CDM protection levels.