Accelerating shortest path computations in hardware

This paper describes an efficient data structure called the Bucket-Heap (BH) for accelerating the widely employed Dijkstra's shortest path algorithm in hardware. We adopt an architecture model consisting of a computational core and memory unit that maintains the network topology. It has been shown that the proposed data structure leads notable reduction in the memory I/O accesses required to perform shortest path computations. Memory I/O upper bounds for the proposed implementation have been established and the analyses reveal that the BH implementation leads to an improvement in excess of 30% when compared with the Naïve implementation of the Dijkstra's algorithm. Moreover, the memory requirements increase only marginally for the BH implementation when compared with that required by the Naïve Dijkstra's implementation.